Please use this identifier to cite or link to this item: http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/5494
Title: FPGA Implementation of Arithmetic Operations Using Quaternary Signed Digit
Authors: Radhika
Jain, Shruti [Guided by]
Keywords: Digital system
Quaternary signed digit
Binary coded decimal
Very large scale integration
Issue Date: 2017
Publisher: Jaypee University of Information Technology, Solan, H.P.
Abstract: The primary problem in digital world is to minimize the area and increase the speed of operations. Using efficient techniques we can overcome these problems. In digital circuits arithmetic operations are very useful and important. Digital circuits are used in microcomputers, signal processing and many other digital systems. Digital system use binary number system which has two states. Binary is represented by binary digit '1'and '0' ,which represents the two different voltage levels HIGH and LOW . The HIGH voltage level is used to represent 1 and LOW voltage is used to represent 0.A microprocessor is a VLSI device that performed arithmetic operations and many other operations. The microprocessor is used as the central processing unit in microcomputers system so speed of the microprocessor depends upon the maximum speed to accomplish the operations. However, propagation time delay, and circuit complexities are the crucial problems in arithmetic operations. For quick results in digital processor we have to increase the speed of the operation. In binary number system, generation of carry in arithmetic operations create delay problems, reduce the speed of microcomputers and increase the complexity of circuits. The problems of arithmetic operations can be overcome by using Quaternary Signed Digit (QSD) number system rather than binary number system.QSD is a higher radix number system, it implies that higher radix number system is less complex than the lower radix number system. QSD is represented by four decimal number 0,1, 2 and 3. QSD perform carry free addition, borrow free subtraction and multiplication which reduce the complexity of circuit and has less delay than other arithmetic circuits.
URI: http://ir.juit.ac.in:8080/jspui//xmlui/handle/123456789/5494
Appears in Collections:Dissertations (M.Tech.)

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