FPGA implementation of collateral and sequence pre-processing modules for low power ECG denoising module

Abstract

ECG signal recording easily suffers from interferences in the environment, such as patient movement, and position of electrodes. For primary diagnosis, doctors need noise-free ECG signals. This paper presents the hardware implementation of denoising of ECG signals using various types of linear windowing techniques and non-linear discrete wavelet transform (DWT) on the proposed architectures using FPGA. DWT has extensive usage in different image processing applications as image compression and information hiding. The simulation results obtained from various techniques and architectures are compared using MATLAB and XILINX VIVADO EDA tools. The performance evaluation of the proposed methodology is evaluated on the basis of resource utilization and on-chip power consumption on the different FPGA boards (Virtex, Kintex, and Zedboards) using VIVADO. From the simulation results, inference has been drawn that Haar wavelet consumes only 0.76% of LUTs, 5.03% of slice registers and 6.7% of DSPs in comparison with other wavelet and window techniques using Zedboard. The Haar wavelet based pre-processor design only consumes 136 mW of on-chip power. The proposed pre-processing module can be used in wearable and portable biomedical equipments.