Please use this identifier to cite or link to this item: http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9187
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dc.contributor.authorSarma, Rajkumar-
dc.contributor.authorBhargava, Cherry-
dc.contributor.authorDhariwal, Sandeep-
dc.contributor.authorJain, Shruti-
dc.date.accessioned2023-01-14T04:23:37Z-
dc.date.available2023-01-14T04:23:37Z-
dc.date.issued2019-
dc.identifier.urihttp://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9187-
dc.description.abstractIn the era of digital signal processing, such as graphics and computation systems, multiplication is one of the prime operations. A multiplier is a key component in any kind of digital system such as Multiply-Accumulate (MAC) unit, various FFT algorithms, etc. The efficiency of a multiplier is mainly dependent upon the speed of operation and power dissipation of the circuit along with the complexity level of the multiplier. This paper is based on Universal Compressor based Multiplier (UCM), which yields a high-speed operation with comparative power dissipation; hence, the enhanced performance is reported. The novel design of UCM is analyzed using Cadence Spectre tool in 90nm CMOS technology. Finally, the UCM is implemented using Nexys-4 Artix-7 FPGA board. The novel design of UCM has demonstrated significant improvement in terms of delay, which is explored in this paper.en_US
dc.language.isoenen_US
dc.publisherJaypee University of Information Technology, Solan, H.P.en_US
dc.subjectCompressor designen_US
dc.subjectNexys-4 Artix-7 FPGAen_US
dc.subjectDelay optimizationen_US
dc.titleUCM: A Novel Approach for Delay Optimizationen_US
dc.typeArticleen_US
Appears in Collections:Journal Articles

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