Please use this identifier to cite or link to this item: http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9171
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dc.contributor.authorPunhani, Akash-
dc.contributor.authorKumar, Pardeep-
dc.contributor.authorNitin, Nitin-
dc.date.accessioned2023-01-13T09:30:00Z-
dc.date.available2023-01-13T09:30:00Z-
dc.date.issued2017-
dc.identifier.urihttp://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9171-
dc.description.abstractAbstract—Interconnection Network is the key component of the digital system. The numbers of cores are increasing on the single chip, which led to the introduction of layered based concept in the System on Chips. Various topologies suggested in the past were based on the 3-dimensional layouts. In this paper, we have proposed using the modified Diagonal mesh topology for defining the single layer of the topology. The proposed topology has been tested on the various traffic patterns like a uniform, bit complement, neighbor, tornado, bit traversal and bit reversal traffic. The performance of the proposed topology was better in the bit reversal traffic. The topology was found to be comparable to other three-dimensional topologies on the uniform, and tornado traffic. The performance of the topology was less in comparison to other topologies in the case of other traffic. Based on the analysis of results it can be observed, we can use the topology in the applications where traffic is following the pattern of the form bit reversal.en_US
dc.language.isoenen_US
dc.publisherJaypee University of Information Technology, Solan, H.P.en_US
dc.subjectLatencyen_US
dc.subjectMesh Interconnection Networken_US
dc.subjectNetwork Trafficsen_US
dc.titleThree-Dimensional Topology based on Modified Diagonal Mesh Interconnection Networken_US
dc.typeArticleen_US
Appears in Collections:Journal Articles

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