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http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9024Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Thakur, Garima | - |
| dc.contributor.author | Sohal, Harsh | - |
| dc.contributor.author | Jain, Shruti | - |
| dc.date.accessioned | 2023-01-09T05:28:12Z | - |
| dc.date.available | 2023-01-09T05:28:12Z | - |
| dc.date.issued | 2018 | - |
| dc.identifier.uri | http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9024 | - |
| dc.description.abstract | In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Jaypee University of Information Technology, Solan, H.P. | en_US |
| dc.subject | Fast Fourier Transform | en_US |
| dc.subject | Kogge Stone Adder | en_US |
| dc.subject | Wallace multiplier | en_US |
| dc.subject | Xilinx ISE | en_US |
| dc.title | High Speed Radix-2 Butterfly Structure using Novel Wallace Multiplier | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Journal Articles | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| High Speed Radix-2 Butterfly Structure using Novel Wallace Multiplier.pdf | 350.88 kB | Adobe PDF | View/Open |
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