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http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/8998| Title: | Accelerated PVT Analysis of UCM Architecture using Cadence ADE-XL |
| Authors: | Sarma, Rajkumar Bhargava, Cherry Jain, Shruti |
| Keywords: | Multiplier Compressor design High speed Cadence Virtuoso PVT analysis Delay optimization |
| Issue Date: | 2019 |
| Publisher: | Jaypee University of Information Technology, Solan, H.P. |
| Abstract: | A Process-Voltage-Temperature (PVT) Variation check is run on the novel Universal Compressor based Multiplier (UCM) architecture, which promises for fast multiplication in ultra-low supply voltages (less than 0.9 V) for higher order operation. The analysis further shows that for 5x5 bit & 9x9 bit operation with supply voltage as low as 0.6 V, the delay has reduced by 0.73% & 5.05% (mean values) respectively than Wallace tree multiplier architecture. The analysis is carried out in Cadence Spectre tool using ADE-XL at CMOS 90 nm technology. |
| URI: | http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/8998 |
| Appears in Collections: | Journal Articles |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Accelerated PVT analysis of UCM architecture using Cadence ADE-XL.pdf | 788.09 kB | Adobe PDF | View/Open |
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