FPGA implementation of Power-Efficient ECG pre-processing block

Abstract

The hardware implementation of a low power digital system design is proposed to pre-process the Electrocardiogram (ECG) using an FPGA board. The system implementation of the pre-processing module consists of removal of two prominent noises namely Electromyography and Base Line Wander using two different types of filters comprising Low Pass Filter and High Pass Filter. Model-Based design of Finite Impulse response filter is implemented using Xilinx System Generator targeting ZedBoard Zynq-7000 evaluation board using XILINX VIVADO tool. To obtain the optimized resource utilization and power consumption various conventional windows has been compared. Kaiser and Bartlett's window shows the best performances as it utilizes only 0.41% of LUT and 0.37% of registers. These windows also consume only 35 mW of power in contrast to other windowing methods. The hardware implementation of the selected pre-processing module will be used in wearable and portable ECG module in the future.