Energy Efficient Approximate Architecture for Error Tolerant Applications

Abstract

The energy-efficient circuits are one of the primary/major problems in many different areas of digital design, including embedded and battery-driven devices as well as data centers. During the last several years, wide variety of strategies have been developed with the goal of reducing the amounts of power and increasing the speed. One of these developing techniques that aims to make error-tolerant/resistant applications is called approximate computing, and it offers some exciting potential advantages. The traditional/conventional power vs performance trade-offs are expanded to include a third orthogonal dimension, that is introduced by approximate computing: design correctness. The fundamental idea behind such an approach is that if one relaxes the accuracy requirement on the output, they can realize significant savings in the hardware design metrics such as power consumption, design area, and critical path delay. This is the underlying principle that underpins such an approach. This paradigm, on the other hand, can only be used in contexts where there is already an established tolerance for relatively inconsequential and minor mistakes. Several examples of potential applications include those in the fields of media processing, machine learning, and data mining. It is interesting to note that in recent years, there has been a rise in the number of applications that rely heavily on data and machine learning, yet the importance of approximate computing has only increased/grown. Computing based on approximations is becoming more popular as a computing paradigm for applications in computer vision, data analytics, and image/signal processing. The use of approximate computing is becoming more important/crucial in the current age of real-time applications. Adders are the primary component for the design and implementation of digital circuitry and signal processing applications in many different types of computers, including Digital Signal Processors (DSP) and microprocessors. The propagation delay in the carry chain is the primary issue that must be addressed while adding. The length of the carry chain increases with increase in bit-width of the input operands is stretched out more. The most effective adder designs for Very Large Scale Integration (VLSI) are categorized as having a Parallel Prefix (PPx) adder structure. This is done to alleviate the carry propagation issue that occurs in digital systems. In this thesis, a unique approach is provided for implementing and synthesizing various PPx adders (both non-speculative and speculative) for any Application Specific Integrated Circuit (ASIC) based system. When compared to the most recent generation of approximate adders, the proposed/suggested Han Carlson speculative PPx adder exhibit superior performance in terms of both power consumption and delay/latency. In comparison to the proposed/suggested Kogge-Stone adder, Brent-Kung adder the performance of the speculative Han-Carlson adder results in a speed increase of 23.79 percent and 46.92 percent respectively. An operand bit-length of 16 bits was taken into consideration while developing the recommended designs. In conclusion, the proposed/suggested adder is validated/tested and shown effective for an error-tolerant image processing application, yielding a PSNR of 41.2 dB. The process of approximation involves making compromises in terms of precision, speed, area, and power consumption. These compromises are important for error-tolerant applications, the ones in which a little reduction in accuracy does not have a significant impact on the final result. In this thesis, a power-efficient approximate multiplier is constructed by using the unique approximation adder, low-order compressor (3:2, 4:2 compressors). In order to accomplish the reduction stage of the partial product while preserving an expectable level of precision that is acceptable, approximate compressors are used. The proposed/suggested approximate multiplier demonstrates increased performance in comparison to the state-of-the-art in terms of the number of Lookup Tables (LUTs), area, speed and power consumption. In order to verify the accuracy of the findings, an approximate multiplier is used in image processing applications, for the purpose of image blending. The proposed approximate multiplier is applied to 2 sets of images. For set 1, PSNR value of 25.49 dB is achieved, and for set 2, PSNR value of 24.7 dB is achieved. Compressors play an important/vital role in the process of multiplication as a component that is responsible for the decrease of the number of partial products. Higher-order approximation compressors with ratios of 5:2, 6:2, 7:2, and 8:2 are also constructed. The proposed set of compressors improves utilizes less area and power consumption in comparison to the conventional/traditional method. These higher-order compressors are used in multipliers reduction steps to increase the performance of the multiplication process with slight compromise in accuracy. When compared to a conventional/traditional multiplier, the performance of multiplication exhibits 37.77 percent and 42.79 percent reduction in power consumption for 8-bit and 16-bit respectively. The technique of multiplication has been applied to the original, the negative, and the sharpened images/pictures by making use of their respective masks. The proposed/suggested multiplier demonstrates a PSNR increase of 51.36 percent (for the original picture), 6.04 percent (for the negative image), and 22.44 percent (for the sharpened image) vice-versa state-of-the-art technique. In this thesis, three different designs for approximate multipliers are proposed: the power optimized approximate Multiplier (POM), area optimized approximate Multiplier (AOM), and a power & area optimized approximate Multiplier (PAOM). Speculative Han Carlson adder and compressor-based multiplier blocks are used in the implementation of these designs. In the final addition step of each of the three approximate multiplier designs, a Han Carlson adder is used as the fundamental building block for the addition of the final sum. The installation of the energy-efficient approximate multiplier blocks requires the employment of a variety of compressors. VIVADO 2018.3 Design Tool is used to carry out each and every simulation. Additionally, the proposed adders and multipliers have been validated for the image processing application for image blending.