VLSI Implementation of Adder Circuits Using Quaternary Signed Digit

Abstract

The data manipulating agility is hampered in base 2 cardinal depiction methodology because of reproduction and evolution of trajectory of peculiarly when the cardinal depiction of bits upturns. In this project we have successfully implemented and observed that the carry is generated in the Ripple Carry Adder (RCA) and the Carry Save Adder (CSA) and thus we aim to remove the generated trajectory which we have contended in this work. We face O(n) trajectory breeding lagging n-bit base-2 process. To resolve this complication, signed cipher notation is utilized for trajectory complimentary reckoning engagements. Subtraction without borrow as well as aggregation without trajectory can be implemented using Quaternary Signed Digit (QSD) cardinal depiction methodology. In this work we extend the QSD addition to eliminate trajectory from aggregation and lagged aggregation and we will also work on minimizing the power consumption and lag at a particular frequency. We will also be comparing the reckoning engagements of QSD cardinal depiction methodology with that of base-2 cardinal depiction methodology. For all these delineating and calculations we will be using Xilinx 14.7 software.