Please use this identifier to cite or link to this item: http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/6937
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dc.contributor.authorChadda, Anubha-
dc.contributor.authorSehgal, Vivek [Guided by]-
dc.date.accessioned2022-09-27T10:42:18Z-
dc.date.available2022-09-27T10:42:18Z-
dc.date.issued2019-
dc.identifier.urihttp://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/6937-
dc.description.abstractNetwork on Chip (NoC) is one of the productive on-chip communication architecture for System on Chip (SoC).With the help of NoC large number of computational is done on a single chip NoC. Network-On-Chip discards the use of wire and is focused on the routing of the packets. The main focus of NoC is the reduction in the size of the chip, and making it as small as possible; an efficient algorithm can enhance the performance of NoC. In this thesis, we discussed about Base router, flexible router architecture and routing algorithm(XY and OE).All the simulation done in NIRGAM simulator.en_US
dc.language.isoenen_US
dc.publisherJaypee University of Information Technology, Solan, H.P.en_US
dc.subjectNetwork on Chipen_US
dc.subjectSystem on Chipen_US
dc.subjectAlgorithmen_US
dc.subjectFlexible routeren_US
dc.titleFlexible Router Architecture of Network-On-Chipsen_US
dc.typeProject Reporten_US
Appears in Collections:B.Tech. Project Reports

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