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DC Field | Value | Language |
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dc.contributor.author | Chadda, Anubha | - |
dc.contributor.author | Sehgal, Vivek [Guided by] | - |
dc.date.accessioned | 2022-09-27T10:42:18Z | - |
dc.date.available | 2022-09-27T10:42:18Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/6937 | - |
dc.description.abstract | Network on Chip (NoC) is one of the productive on-chip communication architecture for System on Chip (SoC).With the help of NoC large number of computational is done on a single chip NoC. Network-On-Chip discards the use of wire and is focused on the routing of the packets. The main focus of NoC is the reduction in the size of the chip, and making it as small as possible; an efficient algorithm can enhance the performance of NoC. In this thesis, we discussed about Base router, flexible router architecture and routing algorithm(XY and OE).All the simulation done in NIRGAM simulator. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Jaypee University of Information Technology, Solan, H.P. | en_US |
dc.subject | Network on Chip | en_US |
dc.subject | System on Chip | en_US |
dc.subject | Algorithm | en_US |
dc.subject | Flexible router | en_US |
dc.title | Flexible Router Architecture of Network-On-Chips | en_US |
dc.type | Project Report | en_US |
Appears in Collections: | B.Tech. Project Reports |
Files in This Item:
File | Description | Size | Format | |
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Flexible Router Architecture of Network-On-Chips.pdf | 858.57 kB | Adobe PDF | View/Open |
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