Simulation of Optimum topology and Routing Algorithm for 3D Network on Chip

Abstract

Network on Chip (NoC) inter connection scheme is proposed as a unified solution for the design problems faced in SoC. NoC is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. Network on Chip (NoC) is an appropriate candidate to implement interconnections in SoCs. Increase in number of IP blocks in 2D NoC will lead to increase in chip area, global interconnect, length of the communication channel, number of hops transversed by a packet, latency and difficulty in clock distribution. Despite the higher scalability and parallelism integration offered by Network-on-Chip.(NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs), due to limitations such as high power consumption, high cost communication, and low throughput. Recently, extending 2D-NoC to the third dimension (3D-NoC) has been proposed to deal with these problems. Topology, switching mechanism and routing algorithm are major area of 3D NoC research. In this report, I have discussed three topologies 3d Mesh Topology, 3d Star Topology, 3d Recursive Network Topology(3D-MT, 3D-ST and 3D-RNT) which are derived from their 2d versions and their corresponding routing algorithm for 3D NoC are presented. As 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore,a 3D-NoC system should be fault tolerant to transient malfunctions or permanent physical damages. Therefore I have also discussed low latency, high throughput and fault tolerant routing algorithm named Look Ahead Fault Tolerant (LAFT). I have also discussed an efficient 3-D Asymmetric Torus routing algorithm for NoC. The 3-D torus has constant node degree, recursive structure, simple communication algorithms, and good scalability. A Quadrant-XYZ dimension order routing algorithm is proposed to build 3-D Asymmetric Torus NoC router. All the algorithms are simulated using my very own simulator and the algorithms are compared on the basis of latency, number of hops traversed , energy dissipation and other important factors.