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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Setia, Simran | - |
dc.contributor.author | Chanderwal, Nitin [Guided by] | - |
dc.date.accessioned | 2022-08-26T09:55:08Z | - |
dc.date.available | 2022-08-26T09:55:08Z | - |
dc.date.issued | 2015 | - |
dc.identifier.uri | http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/6004 | - |
dc.description.abstract | Multi-stage Interconnection Networks (MINs) are widely used for broadband switching technology and for multiprocessor systems. Besides this, they offer an enthusiastic way of implementing switches used in data communication networks. With the performance requirement of the switches exceeding several terabits/sec and teraflops/sec, it becomes imperative to make them dynamic and fault-tolerant. A number of techniques have been used to increase the reliability and fault-tolerance of the MINs. MINs are typically used in highperformance or parallel computing as a low-latency interconnection (as opposed to traditional packet switching networks), though they could be implemented on top of a packet switching network. Though the network is typically used for routing purposes, it could also be used as a co-processor to the actual processors for such uses as sorting; cyclic shifting, as in a perfect shuffle network; and bitonic sorting | en_US |
dc.language.iso | en | en_US |
dc.publisher | Jaypee University of Information Technology, Solan, H.P. | en_US |
dc.subject | Multi-stage interconnection networks | en_US |
dc.subject | Fault tolerance | en_US |
dc.subject | Routing algorithm | en_US |
dc.subject | Interconnection network | en_US |
dc.title | GUI Based Simulation of Interconnection Networks | en_US |
dc.type | Project Report | en_US |
Appears in Collections: | B.Tech. Project Reports |
Files in This Item:
File | Description | Size | Format | |
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GUI Based Simulation of Interconnection Networks.pdf | 912.82 kB | Adobe PDF | View/Open |
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