Comparative Study of Topologies in 3D NoC

Abstract

Networks on Chip is a communication subsystem on an integrated circuit(commonly known as ”chip”). As the number of cores and IP blocks integrated on a single chip are increasing day by day, there is a need to design such a topology which proves to be best for communication, satisfying all the quality of service(QoS) parameters such as latency, throughput, link-utilization, loss probability and energy consumption at constant bandwidth required. Till now the topologies are optimized on the basis of cost and design space. Now the target is to minimize the global communication traffic, along with the cost and space. Throughput, latency and energy consumption are the basic parameters to consider communication between modules. Shorter the communication path, lesser is the latency. Power consumption also depends upon the length of wires and data activity. For this reason, 3D Networks-on-Chip is gaining more popularity as compared to 2D Networks-on-Chip. In order to reduce space and cost of the chip, Networkson- Chip tries to reduce the number of connections. But reduction in number of connections lead to lack in functionality during traffic and noise, as lesser the number of communication path between any two nodes more chances of bottleneck, leading to the lack of performance. Keeping all these issues in mind, the main concern is to reduce communication delay keeping size and cost constant. The aim of this research work is to do comparative studies of all the topologies being developed for 3D networks-on-chip, and designing a full fledged new topology which proves to be better than the existing ones in all the senses. This report summarizes the concepts of the existing topologies for the on chip networks and gives overview of how different topologies are beneficial over the other.