PVT Variability Check on UCM Architectures at Extreme Temperature-Process Changes

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DC Field	Value	Language
dc.contributor.author	Sarma, Rajkumar	-
dc.contributor.author	Bhargava, Cherry	-
dc.contributor.author	Jain, Shruti	-
dc.date.accessioned	2022-07-14T09:32:00Z	-
dc.date.available	2022-07-14T09:32:00Z	-
dc.date.issued	2020	-
dc.identifier.uri	http://ir.juit.ac.in:8080/jspui//xmlui/handle/123456789/4200	-
dc.description	DOI: 10.4018/978-1-7998-1464-1.ch013 Copyright © 2020, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.	en_US
dc.description.abstract	The UCM (universal compressor-based multiplier) architecture promises to provide faster multiplication operation in supply voltage as low as 0.6 V. The basic component of UCM architecture is a universal compressor architecture that replaces the conventional Wallace tree algorithm. To extend the work further, in this chapter, a detailed PVT (process-voltage-temperature) analysis is performed using Cadence Virtuoso 90nm technology. The analysis shows that the delay of the UCM has reduced more significantly than the Wallace tree algorithm at extreme process, voltage, and temperature.	en_US
dc.language.iso	en	en_US
dc.publisher	Jaypee University of Information Technology, Solan, H.P.	en_US
dc.subject	Wallace tree algorithm	en_US
dc.subject	process-voltage-temperature	en_US
dc.subject	Cadence Virtuoso	en_US
dc.title	PVT Variability Check on UCM Architectures at Extreme Temperature-Process Changes	en_US
dc.type	Book chapter	en_US
Appears in Collections:	Book Chapters

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